Clustering techniques for coarse-grained, antifuse-based FPGAs
Coarse-grained, antifuse-based FPGAs have emerged as a compelling technology to minimize the performance gaps between FPGAs and ASICs in area, speed, and power dissipation. As the FPGA architectures prefer large, programmable logic blocks, efficient clustering algorithms are vital to make use of the benefits from those advanced architectures. Circuit clustering is an important technique for coarse-grained FPGAs. First, clustering can reduce the complexity of large circuit designs by a significant factor. Second, clustering can improve the quality of the results of other operations such as placement and routing. In this dissertation, clustering techniques for area, delay, and power dissipation are proposed. First, an area-driven clustering algorithm is presented to minimize the number of macro logic cells required to cover a network. This algorithm calculates the minimum number of the logic cells by a multi-dimensional coin-change problem or a linear programming formulation. Subsequently, with the minimum number of available macro logic cells, actual clustering, which packs nodes into clusters, is performed to improve routability and delay. Next, a timing-driven clustering algorithm is presented to minimize the number of macro logic cells on the longest input-output path. The algorithm optimally labels nodes for the smallest delay and then minimizes redundant logic replication by using slack-time relaxation during the clustering phase. Finally, a low-power clustering algorithm is presented to minimize power dissipation with the minimum logic replication. The algorithm accurately emulates logic replication to estimate the cost incurred by logic replication to meet timing constraints. Based on this information, the proposed algorithm substantially reduces size of the replicated logic, resulting in benefits in area, delay, and power dissipation.